I am currently pursuing my Ph.D. from the Department of Computer Science & Engineering at the Indian Institute of Technology Kanpur. I am working under the guidance of Dr. Debapriya Basu Roy. My research area includes Hardware Accelerator Design and Hardware Security.

During my Ph.D. I am working on Hardware implementation and acceleration of Post Quantum Cryptographic Algorithms. I have also worked on design and implementation of Physically Unclonable Functions (PUF) and building security protocols using PUFs.

I have completed my M.Tech in Computer Science and Engineering from University of Kalyani, West Bengal, India.. My M.Tech thesis was supervised by Dr. Anirban Mukhopadhyay and Dr. Sujoy Chatterjee. I received my B.E in Computer Science and Engineering from University Institute of Technology, Burdwan University.

Also, I worked as a JRF (Junior Research Fellow) at National Institute of Technology Durgapur on the project "Design of Lightweight and Cost-effective secure architecture for authentication and FPGA applications", supervised by Dr. Bibhash Sen.

• Delivered state-of-the-art seminar at IIT Kanpur titled "Hardware Acceleration and Side-Channel Attacks on Post-Quantum Cryptography.".
• Accepted for publication - Suraj Mandal and Debapriya Basu Roy "Winograd for NTT: A Case Study on Higher-Radix and Low-Latency Implementation of NTT for Post-Quantum Cryptography on FPGA". IEEE Transactions on Circuits and Systems I (IEEE TCAS-I).
• Accepted for publication - Suraj Mandal and Debapriya Basu Roy "Design of a Lightweight Fast Fourier Transformation for FALCON using Hardware-Software Co-Design" (GLSVLSI 2024).