I am currently pursuing my Ph.D. from the Department of Computer Science & Engineering at the Indian Institute of Technology Kanpur. I am working under the guidance of Dr. Debapriya Basu Roy. My research area includes Hardware Accelerator Design and Hardware Security.

During my Ph.D. I am working on Hardware implementation and acceleration of Post Quantum Cryptographic Algorithms. I have also worked on design and implementation of Physically Unclonable Functions (PUF) and building security protocols using PUFs.

I have completed my M.Tech in Computer Science and Engineering from University of Kalyani, West Bengal, India.. My M.Tech thesis was supervised by Dr. Anirban Mukhopadhyay and Dr. Sujoy Chatterjee. I received my B.E in Computer Science and Engineering from University Institute of Technology, Burdwan University.

Also, I worked as a JRF (Junior Research Fellow) at National Institute of Technology Durgapur on the project "Design of Lightweight and Cost-effective secure architecture for authentication and FPGA applications", supervised by Dr. Bibhash Sen.

• Accepted for publication - Suraj Mandal and Debapriya Basu Roy "Design of a Lightweight Fast Fourier Transformation for FALCON using Hardware-Software Co-Design" (GLSVLSI 2024).
• Selected as a recipient of Prime Minister's Research Fellowship (PMRF) Cycle 11.
• Accepted for publication - Suraj Mandal and Debapriya Basu Roy "A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA" International Conference on VLSI Design (VLSID 2024).
• Accepted for publication -Harish Prasad Alam, Suraj Mandal, Debapriya Basu Roy. "How to Multiply: A Comparative Analysis between Karatsuba, Toom-Cook and NTT Multiplier for Polynomial Multiplication in NTRU". (AsianHOST 2023)